Veriflow Cc

VeriFlow-CC: A Claude Code-driven RTL design pipeline. Automates Chip-on-Chat from architecture to synthesis (iVerilog/Yosys) using a stateful, zero-dependency LLM orchestration skill. Features sub-agent nesting for code gen and behavioral-driven verification.

# VeriFlow-CC **Claude Code-driven RTL design pipeline** — zero Python dependencies, Claude Code main session is the driver. ## What It Is VeriFlow-CC treats Claude Code as the pipeline brain: the main Claude Code session controls stage transitions, calls a sub-agent for RTL generation, and handles errors and rollbacks. Differences from the full VeriFlow-Agent: - No LangGraph / LangChain / Streamlit - No `pip install` required - Claude Code itself is the interaction and decision layer - State persisted to JSON, recoverable after session restart ## Architecture ``` User types /vf-rtl <pro

When to use

Community skill by bjwanneng. Install from: https://github.com/bjwanneng/veriflow-cc

Examples

Sub-agent returns "0 tool uses"

Ensure the agent's `tools` field uses comma-separated capitalized names:

iverilog returns exit code 127

iverilog needs its internal drivers (`ivlpp`, `ivl`) which live in `lib/ivl/`. The pipeline auto-discovers and saves these paths. Verify with:

Simulation passes but pipeline reports FAIL

The sim hook uses strict 3-layer verification: (1) sim.log must be non-empty, (2) no `[FAIL]` or `FAILED:` lines, (3) must contain `ALL TESTS PASSED`.